1. Field of the Invention
This invention relates to a gate input circuit for transistor circuits constituted with insulated gate field effect transistors, and more particularly to a gate input circuit for semiconductor integrated circuits which prevents a gate insulator of an insulated gate field effect transistor from being broken down.
2. Description of the Prior Art
Generally speaking, in an insulated gate field effect transistor (hereinafter referred to as a field effect transistor) whose gate has a high capacitive input impedance, an unexpected electric charge of even a slight quantity induced a high voltage and caused dielectric breakdown of the gate electrode.
Accordingly, in a semiconductor integrated circuit including the field effect transistors, such a field effect transistor as connected to respective external terminals of an output signal line, power line and earth line and thus connected, between its gate and source electrodes or between its gate and drain electrodes, in parallel with other parasitic capacitances, PN-junction elements or other circuit elements bears a large parallel capacitance across its gate and source electrodes or its gate and drain electrodes and a small resistance as well so that the adverse high surge voltage will not induce a high voltage across the gate capacitance of the field effect transistor in question and there is no need to look into the problem on the dielectric breakdown of gate electrode. On the contrary, such a field effect transistor as directly connected at its gate electrode to an external terminal of semiconductor integrated circuit or connected at either its drain or source electrode to the external terminal of the same, and also connected, between its gate and source electrodes or between its gate and drain electrodes, to none of circuit elements bears a slight capacitance as viewed from the external terminal and a high resistance so that the gate insulator of field effect transistor tends to be broken down.
Especially, where an input signal to a logic circuit including field effect transistors formed in a semiconductor integrated circuit is generated in terms of a binary level of 1 and 0 by means of an external mechanical switch such as a key beard switch incorporated in a semiconductor integrated circuit of a key input circuit for an electronic desk calculator, the key switch is directly connected to a gate electrode of a field effect transistor constituting an input stage inverter through which the input signal is transmitted. Accordingly, in accordance with the switching of the key switch, the gate input circuit of the field effect transistor constituting the input stage inverter is intermittently brought into a floating condition at which the gate input circuit to the field effect transistor suffers from disadvantages in circuit operation such as erroneous operation due to noise and tendency to inducing an adverse high surge voltage. More particularly, before a completed semiconductor integrated circuit is incorporated into the electronic desk calculator set, the external input terminal to be connected with the key switch of the semiconductor integrated circuit is brought into the floating condition and accordingly, a surge voltage resulting from an unexpected transient condition due to the generation of an electrostatic charge during handling of the semiconductor integrated circuit does damage to the gate insulator of the field effect transistor. In consequence, circuit operation over the whole of semiconductor integrated circuit is disabled.
In order to prevent the floating of the gate input circuit of the field effect transistor to which the mechanical or key switch is connected, an expedient may be taken wherein another field effect transistor is combined with the mechanical switch in question. Even with this expedient, there arises a problem that a gate insulator of the combined field effect transistor is broken down.